1. Field of Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to a Vertical Super-Thin Body Field Effect Transistor (VSTB-FET) made of Semiconductor-On-STI-Wall structure and its methods of fabrication.
2. Discussion of Related Art
In order to increase the device performance, silicon on isolator (SOI) transistor has been proposed for the fabrication of modern integrated circuits. FIG. 1 illustrates the standard fully depleted (FD) silicon on isolator (SOI) MOSFET transistor (FD SOI MOSFET) 1000. The transistor 1000 includes a single crystalline silicon substrate 1020 having an insulating layer 1040, such as a buried oxide formed thereon. A single crystalline silicon body 1060 is formed on the insulating layer 1040. A gate dielectric layer 1080 is formed on the single crystalline silicon body 1060 and a gate electrode 1100 formed on the gate dielectric 1080. Source 1120 and Drain 1140 regions are formed in silicon body 1060 along laterally opposite sides of the gate electrode 1100.
From device physics it is clear that the body should not be doped which makes the drive current (Ion) of this device and other performance parameters beneficial. With no doping in the body only the electrostatic control is the mechanism for Vth and leakage control. To control the channel and provide low subthreshold leakage (Ioff) the thickness of the body (Tsi) is to be about ⅓ of the channel length. For practical purposes if one needs to make 15 nm channel length (Lg) Tsi is to be about 5 nm. As of now it is practically impossible to make a SOI wafer of 300 mm with 5 nm silicon body thickness and thickness variability across wafer about 5% (0.25 nm which is less than a single atomic layer of silicon lattice). This is the reason why such an approach has no scalability advantages.
A double gate (DG) FD SOI MOSFET device based on SOI FinFET structure, such as shown in FIG. 2 has been proposed to alleviate the silicon thickness control issue. The double gate (DG) device 2000 includes a silicon body 2020 formed on an insulating substrate 2040. A gate dielectric 2060 is formed on two sides of the silicon body 2020 and a gate electrode 2080 is formed adjacent to the gate dielectric 2060 formed on the two sides of the silicon body 2020. A sufficiently thick insulating layer 2090, such as silicon nitride, electrically isolates the gate electrode 2080 from the top of silicon body 2020.
The device 2000 essentially has two gates, one on either side of the channel of the device. Because the double gate device 2000 has a gate on each side of the channel, thickness (Tsi) of the silicon body can be double that of a single gate device and still obtain a fully depleted transistor operation. That is, with a double gate device 2000 a fully depleted transistor can be formed where Tsi=(2*Lg)/3. The most manufacturable form of the double gate (DG) device 2000, however, requires that the body 2020 patterning be done with photolithography that is 0.7× smaller than that used to pattern the gate length (Lg) of the device. Although, double gate structures double the thickness of the silicon film (since there is a gate on either side of the channel) these structures, however, are very difficult to fabricate for a practically usable aspect ratio. For example, silicon body 2020 requires a silicon body etch which can produce a silicon body 2020 with an aspect ratio (height to width) of about 5:1. Low performance achieved for more than 10 years of efforts, higher price per wafer for SOI and Floating body effects to be more pricy to address in designing any integrated circuitry all together have made the industry reluctant to work hard on the implementation of high aspect ratio double gate FinFET's.
A bit of improvement of the DG SOI FinFET is made as illustrated in FIG. 3a and FIG. 3b where the thick dielectric on the top of the FinFET was made as thin as the gate dielectric and the FinFET called as tri-gate since it has 3 active sides of the Fin as the channel. This innovation makes the effective channel width more beneficial. And it does make it more manufacturable for a practically achievable modest aspect ratio of the Fin to be about 1 to 3. FIG. 3a is a cross-sectional illustration of the semiconductor body and the gate electrode. FIG. 3a illustrates a cross-section taken within the channel region 7000 of the semiconductor body 3000. The metal gate electrode 1000 and a high-k gate dielectric layer 1100 are shown as being formed on three sides of the channel region 7000. The metal gate electrode 1000 and the high-k gate dielectric layer 1100 extend down into the isolation layer 4000 due to recess 8000.
FIG. 3b illustrates 3D view of the Tri-Gate FinFET. The device has a great advantage of having the body electrically connected to the substrate which removes all the circuit design, reliability, and leakage issues related to the floating body SOI UTB and FinFET devices so that it can be used for any high performance and low power application.
Further scaling to below 10 nm channel length which has to have the body thickness of 5 nm and less becomes difficult to fabricate because this three dimensional (3D) tiny Fin standing alone can be broken and/or washed away by cleaning especially when using sonication for better particle removal which is important for cleaning 3D reliefs. Another disadvantage in scaling is that. It is known that when Si body thickness gets below 5 nm the band structure starts depending on the thickness in a device performance improvement favor. Due to the quantum confinement effects the band gap gets wider which provides a higher barrier, significantly less the subthreshold leakage (Ioff) and better Ioff control which in turn allows to go for a more aggressive channel length reduction resulting as a positive side effect to a less temperature dependence of the performance parameters. It should be noted that as long as the body thickness is getting less than 8 nm the second gate from the opposite side and the top narrow gate are losing their effects on the total inversion charge concentration and at 5 nm thickness there is no merit of having double gate structure due to strong overlapping of the 2D inversion carrier layers from both gate sides. It is debatable at this point of the advance device physics knowledge, but mobility must also degrade for a double gate structure due to presence of the strong electric field on both sides. So manufacturing the three gates or double gates becomes more complex without the additional merit of having them.
Furthermore the double gate (or Tri-gate for that matter) is difficult to make with a Fin of a high aspect ratio. The best practically achievable ratio is about 3, which is difficult to increase while scaling the Fin thickness because of a Fin mechanical fragility concern.
In the proposed invention this aspect ratio can easily go to up to 10 or more. Using a single side gate the current achieved per Fin is potentially substantially more than for double-gate or triple gate structures. So a higher current can be achieved per μm-fp (per μm of footprint). The higher aspect ratio should certainly provide better mobility and less interface roughness scattering. This is most important at high inversion regime when Ion is measured as the most important performance parameter. Heat dissipation from the channel also becomes easier due to 4× less power density per physical μm width is generated. An important aspect of the Double-Gate architecture (and tri-gate for that matter) is that when the inversion layers are overlapped forming a single 2D-carrier gas, screening of the electric field from both sides doubles the carrier concentration in the channel. This has a few consequences:    1. Much higher electron-electron (hole-hole) scattering resulting in reduction of the mobility and the ballistic velocity;    2. Every carrier is now scattered by the interface roughness from both sides which again results in less mobility;    3. It is a very well known fact that usage of the high-k results in less mobility due to higher interface traps (Dit), soft-phonon scattering, and large intrinsic charge in high-k materials. So having the high-k on both sides of the body for the single inversion layer is certainly not beneficial for device performance.
As can be seen in a paper by Auth C. (see list of referenced papers above) the Fin is made with rather large tilts on both sidewalls suggesting that it is not simple even for the precision of Intel's technology to make it more vertical or ultimately ideal vertical Fin interfaces. This results in a few consequences:    1. Scaling of such a sloppy Fin goes to its limit when thinning at the bottom results in over-etching the tip and the Fin-height/Fin-thickness aspect ratio is self-limited;    2. Fin aspect ratio can not be large enough due to bringing a large variation of the body thickness and the threshold voltage (Vth) as a result of it and the thinner the Fin the more Vth variability comes about for the same relative variability;    3. Such a sloppy Fin results in a Vth changing along the Fin height leading to much less electrostatic control at the Fin bottom vs. the top. So a higher sub-Vth leakage (Ioff) is expected that limits the scaling;    4. It is well known that the sloppy Si surface will have a high interface trap density (Dit) which in turn brings a high GIDL current problem (not addressed in Auth's paper because of the leakage due to the consequence 3 above, which is likely over-shadowing the GIDL).
Rather low Ion current performance for both nMOSFET and pMOSFET published in Auth's paper suggests that these considerations above are likely correct and significant, especially accounting for such large efforts to reduce the parasitic resistance which might result that the total performance is indeed limited by the channel mobility.
Performance variability shown in Auth's paper is also needed to be better by at least 50% for Vth to be about 50 mV not 100 mV as of now.
There is a need, therefore, for a MOSFET transistor, which can be scalable and has better performance than DG or tri-gate transistors.